Metal interconnections of semiconductor devices may connect circuits formed in a semiconductor substrate. Circuits may be connected through electrical connections and/or pad connections between semiconductor devices. Connections may include metal thin films (e.g. aluminum, aluminum alloys, and/or copper). Critical dimensions (CD) of interconnections may be relatively small in highly integrated devices. A damascene process may be used to form metal interconnections having a micro pattern.
To form a metal interconnection, a diffusion barrier may be formed over a semiconductor layer. A diffusion barrier may include a conductive layer. An inter-metal dielectric (IMD) layer may be formed over a diffusion barrier. A via hole pattern may be formed in an IMD layer. A via hole pattern may be formed using a photoresist layer to pattern a IMD layer. A via hole may be filled with a photoresist layer and a recess process may be performed. A trench pattern may be etched in the IMD layer using a photoresist layer as a mask. A photoresist layer and a trench pattern that fill a via hole may be removed. A cleaning process of removing particles that remain in a via hole and a trench may be performed. A via hole and a trench may be filled with copper.
A metal interconnection may have multi-layer structure. A diffusion barrier may prevent a lower copper metal interconnection from diffusing into an upper IMD layer when a process of forming the upper copper metal interconnection is performed. A diffusion barrier may be formed to have a thickness greater than about 300 Å.
However, a diffusion barrier may be affected by a process of removing a photoresist layer that fills a via hole. If a via hole is non-uniformly etched, a lower copper metal interconnection may be exposed to the air during a cleaning process. If a lower copper metal interconnection is exposed to air, it may be corroded. Corrosion may degrade electrical characteristics, which may degrade the reliability of a semiconductor device.